Digital signal processors (DSPs) are commonly used to perform real-time computationally intensive data processing in systems such as modems, digital audio equipment, and digital cellular communications systems. Common features of DSP architectures include an address generation unit (AGU) that implements modulo addressing, program and data memory, a program controller, an arithmetic logic unit (ALU) that implements a multiply-and-accumulate operation, and other application dependent peripheral blocks.
As instruction speeds of DSPs increase, the need to quickly access data in memory for calculations becomes more critical, as the memory accesses must keep pace with the faster instructions. If speed mismatches between instruction execution and slower memory accesses exist, speed improvements in instruction execution will be nullified by the memory access bottleneck.
In microprocessor architectures, average memory access speeds have been improved by providing small cache memories that store a portion of the data in the main memory for faster access. DSPs, however, are data processing intensive and require complex addressing modes that render cache memory solutions unfeasible, as they are unable to support the complex addressing modes and required storage capacity.
Another prior-art technique for increasing the effective speed of memory accesses, or memory access bandwidth, involves accessing parallel memories simultaneously. This technique, however, requires modification of the AGU to support the multiple memories. The modified AGU must be supported by additional control information from the program controller, which further requires modification of the instruction set, redesign of the program controller, etc. These modifications to well-established blocks in a DSP architecture translate into additional design time, reworking of software, and additional die area and cost.
Therefore, a need exists for a method and apparatus for acceleration of the effective speed of memory accesses in a DSP while eliminating the need for modification of existing architectural blocks such as the AGU and program controller.